PE4302 PDF

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This ohm RF DSA provides both parallel and serial CMOS control interface operates on a single 3volt supply and maintains high attenuation accuracy over frequency and temperature.

It also has a unique control interface that allows the user to select an initial attenuation state at power-up. The PE exhibits very low insertion loss and low power consumption. This functionality is delivered in a 4x4mm QFN footprint. RF Digital Attenuator 6-bit, Attenuation: 0.

Flexible parallel and serial programming interfaces? Unique power-up state selection? Positive CMOS control logic? High attenuation accuracy and linearity over temperature and frequency?

Very low power consumption? Single-supply operation? Packaged in a 20 lead 4x4mm QFN Figure 1. Device Linearity will begin to degrade below 1Mhz 2. Note Absolute Maximum in Table 3. File No. Peregrine Semiconductor Corp. Insertion Loss Figure 3.

Attenuation at Major steps 0 35 Attenuation Error Vs. Frequency Figure 7. Attenuation Setting 2 0. Attenuation Setting Figure 9. Attenuation Setting 0. Frequency Figure Input IP3 Vs. Frequency 0. A Table 2. Pin Descriptions Pin No. RF port Note 1. Serial interface data input Note 4. Serial interface clock input. Latch Enable input Note 2. Power supply pin. Power-up selection bit, MSB. Power-up selection bit, LSB.

Ground connection. Attenuation control bit, 8dB. Attenuation control bit, 4dB. Attenuation control bit, 2dB. Attenuation control bit, 1dB. Attenuation control bit, 0. Ground for proper operation Exposed Solder Pad Connection The exposed solder pad on the bottom of the package must be grounded for proper device operation.

Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in Table 3. Specified attenuation error versus frequency performance is dependent upon this condition. Place a 10k? Parallel Mode Interface The parallel interface consists of five CMOScompatible control lines that select the desired attenuation state, as shown in Table 5. Changing attenuation state control values will change device state to new attenuation.

Direct Mode is ideal for manual control of the device using hardwire, switches, or jumpers. Table 5. The Data and Clock inputs allow data to be serially entered into the shift register, a process that is independent of the state of the LE input.

The LE input controls the latch. The shift register should be loaded while LE is held LOW to prevent the attenuator value from changing as data is entered. This feature exists for both the Serial and Parallel modes of operation, and allows a known attenuation state to be established before an initial serial or parallel control word is provided. This allows any one of the 64 attenuation settings to be specified as the power-up state.

Table 6. Serial Interface The serial interface is a 6-bit serial-in, parallel-out shift register buffered by a transparent latch. If use of the internal negative voltage generator is desired, then connect —VDD Black banana plug to ground. If an external —VDD is desired, then apply -3V. J1 should be connected to the parallel port of a PC with the supplied ribbon cable. Using the software, enable or disable each attenuation setting to the desired combined attenuation.

The software automatically programs the DSA each time an attenuation state is enabled or disabled. To evaluate the Power Up options, first disconnect the parallel ribbon cable from the evaluation board.

The parallel cable must be removed to prevent the PC parallel port from biasing the control pins. Evaluation Board Layout Figure Evaluation Board Schematic C0. Serial Interface Timing Diagram Table 7. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fclk specification. Package Drawing 4. Tape and Reel Drawing Pin 1 Table The data sheet contains design target specifications for product development.

Specifications and features may change in any manner without notice. The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information.

No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. Peregrine products are protected under one or more of the following U. Other patents are pending. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product.

Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a PCN Product Change Notice. Peregrine, the Peregrine logotype, Peregrine Semiconductor Corp. All rights reserved.


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